GSH-130A
Analog socket contract; digital management; calibration firmware path; AMS smoke flow; PEX/LVS/ERC/PVT collateral.
Qualified releaseReview integration, qualification and reusable infrastructure.
Editorial selection by documented role and evidence priority. Membership does not establish mutual compatibility; inspect exact releases in the composer.
Analog socket contract; digital management; calibration firmware path; AMS smoke flow; PEX/LVS/ERC/PVT collateral.
Qualified releaseDigital user socket; GFI; management; reset isolation; DMA; trace; DFT; GPIO/debug; physical contract.
Qualified releaseGTI/GTG; data, management and lifeboat fabrics; analog service; power/clock/reset; security/RAS; GDI
Controlled physical releaseAutomotive CAN controller architecture for message processing, timing and host integration.
Evaluation packageAutomotive I/O — 8-channel autonomous LIN controller
Evaluation packagePCIe controller and PHY-control integration architecture, with protocol and electrical qualification scoped to the exact release.
Evaluation packageMixed Signal — fractional-N / digitally assisted PLL platform
Evaluation packageAdaptive serializer/deserializer control architecture; electrical rate and signal-integrity qualification are separate.
Evaluation packageUSB router and PHY-control architecture with a release-specific compliance and analog boundary.
Evaluation packageLUT/FF/SRAM + GM/CAP/CMP/SW/BIAS + routing + config + BIST/repair/health
Architecture IPPhysically homogeneous GCE array; mixed-signal compile; partial reconfiguration; self-characterization/self-healing
Architecture IPVersioned profiles, interoperability and standards-facing evidence
Architecture IPCompletion/fault/health/topology/threshold events
Architecture IPBounded request/response; errors; timeout; versioned CSR contract
Architecture IPTimestamp/source/event/severity/payload; cross-die correlation
Architecture IPPortable APIs to memory, clock, I/O, power, sensor, security, analog, D2D, ESD and package IP
Architecture IPEntitlements, feature rights, device/IP license state and authorization
Architecture IPQualification plans, evidence, limits and certification status bound to exact releases
Architecture IPMulti-slot GFI; queue/DMA fabric; streaming; per-slot reset; fault containment; telemetry; trace; DFT; physical slot contracts.
Core precheck closedManufacturing/post-silicon test, characterization, diagnostics and test evidence
Architecture IPData, management, test, analog, power/clock/reset and security service boundary
Architecture IPGenerated GFI/CSR/DMA/event/trace/DFT/health wrapper
Architecture IPCapability, health, topology, security, utilization and route-cost graph
Architecture IPService constraints; channel model; profile search; power/latency/BER cost; fallback profiles
Architecture IPTraining; measurement; dual-path RX; profile switching; health; failover; analog primitive API
Architecture IPSplit/gang/redundant/instrumentation modes; cell health; spare/quarantine
Architecture IPProof-node vehicles and immutable silicon/physical evidence
Engineering programStart with a chip, a software release or a single IP block.