SPATIAL HETEROGENEOUS COMPUTING
MSR-X130

Intelligence in the layout. Not just the logic.

Specialized compute shaped around routing, memory and the realities of mature-node silicon.

MSR-X130 architectural concept visualization; not fabricated silicon

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

SpatialFusion processing elements
LocalSRAM-oriented execution
Route-awareMature-node architecture

Put the work where it belongs.

MSR-X130 uses a route-aware spatial architecture with fusion processing elements, transport, local SRAM and descriptor-driven movement. Physical constraints are part of the architectural problem.

MSR-X130 / conceptual operation01Describe02Place03Transport04RunArchitectural explanation. Not a floorplan, timing diagram or hardware simulation.Conceptual operation · choose a stage, or play the explanation
Explanatory sequence, not hardware simulation.
Descriptors identify work and data movement.
SEE THE REASON BEHIND THE ARCHITECTURE

A streaming heterogeneous workload

Follow local reuse and explicit data movement across a spatial arrangement. The visual is conceptual and does not replace the frozen physical implementation.

Try a related software workflow
Continue to GSP ↗
01

Fusion processing elements

02

Sparse, solver, vector and floating-point mix

03

Static transport, descriptors and local SRAM

04

R1.0 package-ready implementation

TECHNICAL OVERVIEW

The details matter.

Download the product brief
Canonical identity
IP-045
Responsibility
Flagship heterogeneous spatial superprocessor
Documented building blocks
Fusion processing elements; STF; descriptor/DMA; local SRAM; link; telemetry.
Delivery boundary
Release-specific physical views
Evidence scope
Qualified release
Qualified release

Know the release.
Know what it establishes.

The later R1.0 record identifies MSR-X130 as signoff-complete and ChipIgnite package-ready, with controlled physical/signoff reports and release hashes.

Source basis: Bible v7.42 §§126–127, R1.0 controlled release ledger. This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

Release-specific qualification

The exact mature-node release does not establish advanced-node performance or returned-silicon proof.

Canonical record: Engineering build-spec family

A PATH THAT FITS THE PROJECT

Build with MSR-X130.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

Architecture and release evaluation

Inspect the named release and establish technical fit.

Discuss this scope
production

Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

Discuss this scope
custom

Custom silicon integration

Define the customer-specific work and acceptance criteria.

Discuss this scope

Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.