QUALIFICATION RECORD · IP-001
Garmo RISC-V Processor IP
CPU pipeline; cache/memory interfaces; MMU/TLB options; interrupt/debug; FPU/vector options; compiler/software support; verification/formal collateral; hardened physical views.
Public evidence basis
- Stage / release
- Architecture IP
- Evidence
- Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing.
- Source
- Bible v7.42 IP-001
- Process
- Release-specific / not generalized
- PDK
- Release-specific / not generalized
- External qualification
- Not asserted by this website release