---
title: NPJ-S130 | Garmo Labs
url: https://garmolabs.com/silicon/npj-s130
description: A route-aware solver and accelerator architecture with decomposable processing, Boolean co-execution and deterministic transport.
---

Deterministic route-aware solver/accelerator validation superprocessor

NPJ-S130

# Every operation. A deliberate path.

A route-aware solver and accelerator architecture with decomposable processing, Boolean co-execution and deterministic transport.

Get closer to the architecture

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

Work graphs Execution description

NPJ-STF Transport architecture

FPE Decomposable compute

A CLOSER LOOK

## One architecture.
More ways to see it.

Explore the package study, inspect the detail, or separate the architectural layers. Every view is conceptual.

NPJ-S130 ARCHITECTURAL STUDY

Product study · Architectural concept. Geometry and component counts are illustrative, not physical specifications.

## Compute shaped by movement.

A route-aware solver and accelerator architecture with decomposable processing, Boolean co-execution and deterministic transport.

Conceptual operation · choose a stage, or play the explanation

Explanatory sequence, not hardware simulation.

The descriptor/work-graph ISA describes the execution structure.

SEE THE REASON BEHIND THE ARCHITECTURE

### Solver and EDA datapaths

Follow a work graph through processing and transport. Use the related planner to inspect resource constraints; it does not execute NPJ silicon.

[Try a related software workflow](https://garmolabs.com/demos/dieweaver?product=silicon-ip-079)

The example uses supplied synthetic resources; it is not a simulation or benchmark of NPJ-S130.

[Continue to GSP ](https://garmolabs.com/gsp/workbench?product=silicon-ip-079)

01

Decomposable FPE and Boolean co-execution

02

NPJ-STF deterministic transport

03

Descriptor/work-graph ISA and execution engine

04

Solver/EDA datapaths and sparse zero-skip

TECHNICAL OVERVIEW

## The details matter.

[Download the product brief](https://garmolabs.com/static/briefs/silicon-ip-079.pdf)

Canonical identity

IP-079

Responsibility

Deterministic route-aware solver/accelerator validation superprocessor

Documented building blocks

Decomposable FPE; Boolean co-execution; NPJ-STF; descriptor/work-graph ISA and engine; solver/EDA datapaths; sparse zero-skip; architecture generator/search; verification/evidence framework.

Delivery boundary

Architecture

Evidence scope

Architecture IP

### Before integration.

Preserve the descriptor/work-graph contract when attaching decomposable FPE, Boolean and sparse datapaths to NPJ-STF. Confirm the target clocking, memory, transport and verification configuration for the exact release; do not substitute a generic timing result for physical closure.

- Exact SoC/top and configuration
- Clock, reset, power and pad contract
- Memory, PHY and package dependencies
- Release-specific PVT and signoff views

The selected release must confirm:

- Node/library binding
- Clock/reset limits
- Physical and protocol dependencies
- Artifact hashes
- Acceptance criteria

Unpublished values are not inferred from family names or architecture targets.

[Discuss the integration](https://garmolabs.com/contact?products=silicon-ip-079)

Architecture IP

## Know the release.
Know what it establishes.

Architecture and reusable technology are recorded in the controlled catalog. Request the exact release evidence for your intended integration.

This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

[Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/silicon-ip-079)

### Release-specific qualification

Node-specific physical implementation and system qualification are scoped separately.

Canonical record: Engineering build-spec family

A PATH THAT FITS THE PROJECT

## Build with NPJ-S130.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

### Architecture and release evaluation

Inspect the named release and establish technical fit.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-079&scope=evaluation)

production

### Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-079&scope=production)

custom

### Custom silicon integration

Define the customer-specific work and acceptance criteria.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-079&scope=custom)

## Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.

[Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)