---
title: MSR-X130 | Garmo Labs
url: https://garmolabs.com/silicon/msr-x130
description: A heterogeneous spatial processor designed around the routing, memory and physical realities of mature-node silicon.
---

SPATIAL HETEROGENEOUS COMPUTING

MSR-X130

# Intelligence in the layout. Not just the logic.

Specialized compute shaped around routing, memory and the realities of mature-node silicon.

Get closer to the architecture

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

Spatial Fusion processing elements

Local SRAM-oriented execution

Route-aware Mature-node architecture

A CLOSER LOOK

## One architecture.
More ways to see it.

Explore the package study, inspect the detail, or separate the architectural layers. Every view is conceptual.

MSR-X130 ARCHITECTURAL STUDY

Product study · Architectural concept. Geometry and component counts are illustrative, not physical specifications.

## Put the work where it belongs.

MSR-X130 uses a route-aware spatial architecture with fusion processing elements, transport, local SRAM and descriptor-driven movement. Physical constraints are part of the architectural problem.

Conceptual operation · choose a stage, or play the explanation

Explanatory sequence, not hardware simulation.

Descriptors identify work and data movement.

SEE THE REASON BEHIND THE ARCHITECTURE

### A streaming heterogeneous workload

Follow local reuse and explicit data movement across a spatial arrangement. The visual is conceptual and does not replace the frozen physical implementation.

[Try a related software workflow](https://garmolabs.com/demos/dieweaver?product=silicon-ip-045)

The example uses supplied synthetic resources; it is not a simulation or benchmark of MSR-X130.

[Continue to GSP ](https://garmolabs.com/gsp/workbench?product=silicon-ip-045)

01

Fusion processing elements

02

Sparse, solver, vector and floating-point mix

03

Static transport, descriptors and local SRAM

04

R1.0 package-ready implementation

TECHNICAL OVERVIEW

## The details matter.

[Download the product brief](https://garmolabs.com/static/briefs/silicon-ip-045.pdf)

Canonical identity

IP-045

Responsibility

Flagship heterogeneous spatial superprocessor

Documented building blocks

Fusion processing elements; STF; descriptor/DMA; local SRAM; link; telemetry.

Delivery boundary

Release-specific physical views

Evidence scope

Qualified release

### Before integration.

Shared static transport and descriptor/DMA semantics let specialized engines cooperate under a route-aware architecture. Engine and derivative licensing are scoped independently.

- Exact SoC/top and configuration
- Clock, reset, power and pad contract
- Memory, PHY and package dependencies
- Release-specific PVT and signoff views

The selected release must confirm:

- Node/library binding
- Clock/reset limits
- Physical and protocol dependencies
- Artifact hashes
- Acceptance criteria

Unpublished values are not inferred from family names or architecture targets.

[Discuss the integration](https://garmolabs.com/contact?products=silicon-ip-045)

Qualified release

## Know the release.
Know what it establishes.

The later R1.0 record identifies MSR-X130 as signoff-complete and ChipIgnite package-ready, with controlled physical/signoff reports and release hashes.

This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

[Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/silicon-ip-045)

### Release-specific qualification

The exact mature-node release does not establish advanced-node performance or returned-silicon proof.

Canonical record: Engineering build-spec family

A PATH THAT FITS THE PROJECT

## Build with MSR-X130.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

### Architecture and release evaluation

Inspect the named release and establish technical fit.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-045&scope=evaluation)

production

### Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-045&scope=production)

custom

### Custom silicon integration

Define the customer-specific work and acceptance criteria.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-045&scope=custom)

## Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.

[Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)