---
title: LY-S130 | Garmo Labs
url: https://garmolabs.com/silicon/ly-s130
description: A reasoning and dataflow AI architecture combining matrix/vector execution, attention, sequence state and graph/search resources.
---

General reasoning/dataflow AI superprocessor

LY-S130

# Reasoning has its own rhythm.

A reasoning and dataflow AI architecture combining matrix/vector execution, attention, sequence state and graph/search resources.

Get closer to the architecture

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

LY ISA Programming model

Attention + KV Model state

Collectives Data movement

A CLOSER LOOK

## One architecture.
More ways to see it.

Explore the package study, inspect the detail, or separate the architectural layers. Every view is conceptual.

LY-S130 ARCHITECTURAL STUDY

Product study · Architectural concept. Geometry and component counts are illustrative, not physical specifications.

## Follow the sequence. Keep the state close.

A reasoning and dataflow AI architecture combining matrix/vector execution, attention, sequence state and graph/search resources.

Conceptual operation · choose a stage, or play the explanation

Explanatory sequence, not hardware simulation.

The LY ISA provides the recorded programming model.

SEE THE REASON BEHIND THE ARCHITECTURE

### Stateful model execution

Inspect how attention, sequence state and collective movement relate. Use ModelNative to explore a supplied hardware model, not to infer LY silicon performance.

[Try a related software workflow](https://garmolabs.com/demos/modelnative?product=silicon-ip-071)

The example uses supplied synthetic resources; it is not a simulation or benchmark of LY-S130.

[Continue to GSP ](https://garmolabs.com/gsp/workbench?product=silicon-ip-071)

01

LY ISA and matrix/vector execution

02

Attention, sequence and sparse engine roles

03

KV state and graph/search resources

04

Collectives and GarmoLink-LY integration

TECHNICAL OVERVIEW

## The details matter.

[Download the product brief](https://garmolabs.com/static/briefs/silicon-ip-071.pdf)

Canonical identity

IP-071

Responsibility

General reasoning/dataflow AI superprocessor

Documented building blocks

LY ISA; matrix/vector; attention; sequence; sparse; KV; graph/search; collectives; GarmoLink-LY.

Delivery boundary

Architecture

Evidence scope

Architecture IP

### Before integration.

Map the workload to the supported LY ISA and runtime contract. Bind matrix/vector, attention, sequence, sparse and KV functions to the selected memory organization, then qualify collectives and GarmoLink-LY endpoints for that configuration.

- Exact SoC/top and configuration
- Clock, reset, power and pad contract
- Memory, PHY and package dependencies
- Release-specific PVT and signoff views

The selected release must confirm:

- Node/library binding
- Clock/reset limits
- Physical and protocol dependencies
- Artifact hashes
- Acceptance criteria

Unpublished values are not inferred from family names or architecture targets.

[Discuss the integration](https://garmolabs.com/contact?products=silicon-ip-071)

Architecture IP

## Know the release.
Know what it establishes.

Architecture and reusable technology are recorded in the controlled catalog. Request the exact release evidence for your intended integration.

This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

[Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/silicon-ip-071)

### Release-specific qualification

Node-specific physical implementation and system qualification are scoped separately.

Canonical record: Engineering build-spec family

A PATH THAT FITS THE PROJECT

## Build with LY-S130.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

### Architecture and release evaluation

Inspect the named release and establish technical fit.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-071&scope=evaluation)

production

### Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-071&scope=production)

custom

### Custom silicon integration

Define the customer-specific work and acceptance criteria.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-071&scope=custom)

## Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.

[Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)