---
title: KOURAN | Garmo Labs
url: https://garmolabs.com/silicon/kouran
description: A network-native continuation-token processor with distributed readiness, versioned-object memory and explicit authority boundaries.
---

PROCESSOR / SYSTEM ARCHITECTURE

KOURAN

# Ready. Wherever the work lives.

A network-native continuation-token processor with distributed readiness, versioned-object memory and explicit authority boundaries.

Get closer to the architecture

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

Tokens Continuation model

Versioned objects Memory architecture

Authority Execution boundary

A CLOSER LOOK

## One architecture.
More ways to see it.

Explore the package study, inspect the detail, or separate the architectural layers. Every view is conceptual.

KOURAN ARCHITECTURAL STUDY

Product study · Architectural concept. Geometry and component counts are illustrative, not physical specifications.

## A continuation becomes a connection.

A network-native continuation-token processor with distributed readiness, versioned-object memory and explicit authority boundaries.

Conceptual operation · choose a stage, or play the explanation

Explanatory sequence, not hardware simulation.

Continuation tokens describe work under the architecture’s execution contract.

SEE THE REASON BEHIND THE ARCHITECTURE

### Distributed continuation execution

Inspect how readiness, object state and authority cooperate. The conceptual sequence is a guide to the architecture, not an executed token-processor simulation.

[Try a related software workflow](https://garmolabs.com/demos/dieweaver?product=silicon-ip-3631)

The example uses supplied synthetic resources; it is not a simulation or benchmark of KOURAN.

[Continue to GSP ](https://garmolabs.com/gsp/workbench?product=silicon-ip-3631)

01

Distributed readiness and continuation-token execution

02

Versioned-object memory

03

Authority, epoch, domain and replay enforcement

04

Morphable compute and near-memory ALU contracts

TECHNICAL OVERVIEW

## The details matter.

[Download the product brief](https://garmolabs.com/static/briefs/silicon-ip-3631.pdf)

Canonical identity

IP-3631

Responsibility

Network-native continuation-token processor architecture combining distributed readiness, versioned-object memory, authority/epoch/domain/replay enforcement, morphable compute, near-memory ALU contracts and node/package abstraction.

Delivery boundary

Architecture

Evidence scope

Architecture IP

### Before integration.

Preserve token, object-version, authority, epoch, domain and replay semantics across the selected node/package interface. Bind morphable-compute and near-memory ALU endpoints to the release’s memory/runtime contracts and verify ordering and failure behavior before integration.

- Exact SoC/top and configuration
- Clock, reset, power and pad contract
- Memory, PHY and package dependencies
- Release-specific PVT and signoff views

The selected release must confirm:

- Node/library binding
- Clock/reset limits
- Physical and protocol dependencies
- Artifact hashes
- Acceptance criteria

Unpublished values are not inferred from family names or architecture targets.

[Discuss the integration](https://garmolabs.com/contact?products=silicon-ip-3631)

Architecture IP

## Know the release.
Know what it establishes.

Architecture and reusable technology are recorded in the controlled catalog. Request the exact release evidence for your intended integration.

This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

[Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/silicon-ip-3631)

### Release-specific qualification

Node-specific physical implementation and system qualification are scoped separately.

Canonical record: P1 / IMPLEMENTATION-BACKED ARCHITECTURE

A PATH THAT FITS THE PROJECT

## Build with KOURAN.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

### Architecture and release evaluation

Inspect the named release and establish technical fit.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-3631&scope=evaluation)

production

### Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-3631&scope=production)

custom

### Custom silicon integration

Define the customer-specific work and acceptance criteria.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-3631&scope=custom)

## Keep exploring.

PROCESSOR / SYSTEM ARCHITECTURE

[## RASIN](https://garmolabs.com/silicon/rasin)

An upward-compatible architectural root spanning embedded, real-time, client, server and AI/HPC implementations.

RTL + models

## Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.

[Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)