---
title: KMJ-X130 | Garmo Labs
url: https://garmolabs.com/silicon/kmj-x130
description: CPU, accelerator and memory execution connected through one coherent architecture for demanding mixed compute workloads.
---

COHERENT COMPUTING

KMJ-X130

# Less disconnected. More capable.

CPU, accelerator and memory execution designed to share a computational fabric.

Get closer to the architecture

Architectural concept. Not a die photograph, floorplan or measured-silicon demonstration.

CPU Scalar control

Accelerator Specialized work

Coherence Shared architectural fabric

A CLOSER LOOK

## One architecture.
More ways to see it.

Explore the package study, inspect the detail, or separate the architectural layers. Every view is conceptual.

KMJ-X130 ARCHITECTURAL STUDY

Product study · Architectural concept. Geometry and component counts are illustrative, not physical specifications.

## One coherent view. More ways to compute.

KMJ-X130 brings scalar control, specialized execution and memory together. Coherence and the delivery boundary are specified for the selected implementation, not assumed across arbitrary devices.

Conceptual operation · choose a stage, or play the explanation

Explanatory sequence, not hardware simulation.

CPU execution manages the application and its work.

SEE THE REASON BEHIND THE ARCHITECTURE

### A CPU-led accelerator application

Trace the relationship between host control, shared state and accelerator work. Package, memory and advanced-node implementation options require their own qualification.

[Try a related software workflow](https://garmolabs.com/demos/dieweaver?product=silicon-ip-062)

The example uses supplied synthetic resources; it is not a simulation or benchmark of KMJ-X130.

[Continue to GSP ](https://garmolabs.com/gsp/workbench?product=silicon-ip-062)

01

Coherent CPU + accelerator architecture

02

AI, HPC, graph and network composition

03

Memory/fabric and RAS integration

04

R1.0 package-ready implementation

TECHNICAL OVERVIEW

## The details matter.

[Download the product brief](https://garmolabs.com/static/briefs/silicon-ip-062.pdf)

Canonical identity

IP-062

Responsibility

Extreme-scale superchip

Documented building blocks

Full KMJ CPU/AI/HPC/memory/graph/network stack; chiplet fabric; HBM; RAS/security.

Delivery boundary

Release-specific physical views

Evidence scope

Qualified release

### Before integration.

Use the controlled S130 implementation as a proof and integration foundation. Larger chiplet or high-bandwidth-memory derivatives require their own physical qualification.

- Exact SoC/top and configuration
- Clock, reset, power and pad contract
- Memory, PHY and package dependencies
- Release-specific PVT and signoff views

The selected release must confirm:

- Node/library binding
- Clock/reset limits
- Physical and protocol dependencies
- Artifact hashes
- Acceptance criteria

Unpublished values are not inferred from family names or architecture targets.

[Discuss the integration](https://garmolabs.com/contact?products=silicon-ip-062)

Qualified release

## Know the release.
Know what it establishes.

The later R1.0 record identifies KMJ-X130 as signoff-complete and ChipIgnite package-ready. Its controlled release is distinct from broader family roadmap configurations.

This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.

[Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/silicon-ip-062)

### Release-specific qualification

Package-ready is pre-silicon evidence, not foundry acceptance, returned devices or measured silicon characterization.

Canonical record: Engineering build-spec family

A PATH THAT FITS THE PROJECT

## Build with KMJ-X130.

Technical scope, rights, support and release configuration are agreed before delivery.

evaluation

### Architecture and release evaluation

Inspect the named release and establish technical fit.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-062&scope=evaluation)

production

### Chip / SoC licensing program

Agree deployment or design rights, deliverables and support.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-062&scope=production)

custom

### Custom silicon integration

Define the customer-specific work and acceptance criteria.

[Discuss this scope](https://garmolabs.com/contact?products=silicon-ip-062&scope=custom)

## Your next big idea.
Let’s build it together.

Start with a chip, a software release or a single IP block.

[Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)