---
title: Garmo RISC-V Processor IP qualification | Garmo Labs
url: https://garmolabs.com/qualification/ip-ip-001
description: Garmo Labs chips, software and semiconductor IP.
---

QUALIFICATION RECORD · IP-001

# Garmo RISC-V Processor IP

CPU pipeline; cache/memory interfaces; MMU/TLB options; interrupt/debug; FPU/vector options; compiler/software support; verification/formal collateral; hardened physical views.

[Product page](https://garmolabs.com/ip/garmo-risc-v-processor-ip) [Request exact-release review](https://garmolabs.com/contact?products=ip-ip-001)

## Public evidence basis

Stage / release

Architecture IP

Evidence

Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing.

Process

Release-specific / not generalized

PDK

Release-specific / not generalized

External qualification

Not asserted by this website release

### Qualification boundary

No node-port, silicon-performance, standards certification or analog qualification is inherited from a related product.

Missing process, library, OS, tool or certification data is not inferred from family-level claims.