--- title: GIP2 | Garmo Labs url: https://garmolabs.com/marketplace/families/gip2 description: Garmo Labs chips, software and semiconductor IP. --- IP FAMILY EXPLORER # GIP2 Related canonical identities, organized together. A shared family is not a claim that every release is mutually compatible or equally qualified. [Browse by engineering task](https://garmolabs.com/marketplace/collections) [All IP ](https://garmolabs.com/marketplace) ## 28 named technologies. [All families ](https://garmolabs.com/marketplace/families) Security & trust [## Garmo-AES-256-GCM](https://garmolabs.com/ip/garmo-aes-256-gcm) Multi-context authenticated-encryption datapath architecture. Evaluation package IP-2083 · Source documented Reliability & safety [## Garmo-ASIL-D-Monitor](https://garmolabs.com/ip/garmo-asil-d-monitor) Safety-monitoring island architecture for fault detection, containment and supervised operation; functional-safety certification is not implied. Evaluation package IP-2088 · Source documented Power & control [## Garmo-BMS-ADC](https://garmolabs.com/ip/garmo-bms-adc) Mixed Signal — redundant precision BMS ADC subsystem Evaluation package IP-2089 · Source documented Interfaces & mixed-signal [## Garmo-CAN-FD-CTL](https://garmolabs.com/ip/garmo-can-fd-ctl) Automotive CAN controller architecture for message processing, timing and host integration. Evaluation package IP-2086 · Source documented Memory & storage [## Garmo-CXL-2.0](https://garmolabs.com/ip/garmo-cxl-2-0) Coherent fabric-memory controller architecture with an explicit protocol and physical-interface boundary. Evaluation package IP-2077 · Source documented Memory & storage [## Garmo-DDR5-MC](https://garmolabs.com/ip/garmo-ddr5-mc) Memory — high-throughput DDR5 controller Evaluation package IP-2079 · Source documented Fabric & connectivity [## Garmo-DMA-Engine](https://garmolabs.com/ip/garmo-dma-engine) Coherent DMA architecture for queued data movement and system integration. Evaluation package IP-2095 · Source documented Fabric & connectivity [## Garmo-Ethernet-TSN](https://garmolabs.com/ip/garmo-ethernet-tsn) Time-sensitive Ethernet control, queueing and scheduling architecture. Evaluation package IP-2087 · Source documented Interfaces & mixed-signal [## Garmo-LIN-CTL](https://garmolabs.com/ip/garmo-lin-ctl) Automotive I/O — 8-channel autonomous LIN controller Evaluation package IP-2090 · Source documented Memory & storage [## Garmo-LPDDR5X-MC](https://garmolabs.com/ip/garmo-lpddr5x-mc) Low-power DRAM controller architecture with scheduling and external PHY integration. Evaluation package IP-2080 · Source documented Compute & AI [## Garmo-NPU-1024](https://garmolabs.com/ip/garmo-npu-1024) AI Compute — 1024 tensor-slice cloud/robotics NPU Evaluation package IP-2067 · Source documented Compute & AI [## Garmo-NPU-256](https://garmolabs.com/ip/garmo-npu-256) AI Compute — 256 tensor-slice edge NPU Evaluation package IP-2066 · Source documented Interfaces & mixed-signal [## Garmo-PCIe-5.0-PHY](https://garmolabs.com/ip/garmo-pcie-5-0-phy) PCIe controller and PHY-control integration architecture, with protocol and electrical qualification scoped to the exact release. Evaluation package IP-2076 · Source documented Interfaces & mixed-signal [## Garmo-PLL-Frac](https://garmolabs.com/ip/garmo-pll-frac) Mixed Signal — fractional-N / digitally assisted PLL platform Evaluation package IP-2092 · Source documented Security & trust [## Garmo-PUF-Core](https://garmolabs.com/ip/garmo-puf-core) Security — multi-source silicon PUF root-key subsystem Evaluation package IP-2081 · Source documented Compute & AI [## Garmo-RV32-EC](https://garmolabs.com/ip/garmo-rv32-ec) CPU — high-efficiency RISC-V MCU core Evaluation package IP-2071 · Source documented Compute & AI [## Garmo-RV64-AC](https://garmolabs.com/ip/garmo-rv64-ac) CPU — application-class RISC-V core Evaluation package IP-2072 · Source documented Compute & AI [## Garmo-RV64-GC](https://garmolabs.com/ip/garmo-rv64-gc) CPU — maximum-performance RISC-V core Evaluation package IP-2073 · Source documented Memory & storage [## Garmo-SRAM-Compiler](https://garmolabs.com/ip/garmo-sram-compiler) Memory IP — node-adaptable SRAM compiler architecture Evaluation package IP-2091 · Source documented Security & trust [## Garmo-Secure-Boot](https://garmolabs.com/ip/garmo-secure-boot) Security — post-quantum-ready root of trust and secure boot Evaluation package IP-2084 · Source documented Interfaces & mixed-signal [## Garmo-SerDes-28G](https://garmolabs.com/ip/garmo-serdes-28g) Adaptive serializer/deserializer control architecture; electrical rate and signal-integrity qualification are separate. Evaluation package IP-2093 · Source documented Security & trust [## Garmo-Side-Channel-Guard](https://garmolabs.com/ip/garmo-side-channel-guard) Security — side-channel/fault-resistance execution wrapper Evaluation package IP-2085 · Source documented Compute & AI [## Garmo-Sparsity-ACC](https://garmolabs.com/ip/garmo-sparsity-acc) AI Compute — format-agnostic sparse tensor accelerator Evaluation package IP-2070 · Source documented Security & trust [## Garmo-TRNG-HW](https://garmolabs.com/ip/garmo-trng-hw) Security — high-rate multi-entropy TRNG subsystem Evaluation package IP-2082 · Source documented Compute & AI [## Garmo-Transformer-E](https://garmolabs.com/ip/garmo-transformer-e) AI Compute — dedicated transformer attention/MoE engine Evaluation package IP-2069 · Source documented Fabric & connectivity [## Garmo-UCIe-D2D](https://garmolabs.com/ip/garmo-ucie-d2d) Die-to-die controller architecture for chiplet integration; PHY and standards qualification are release-specific. Evaluation package IP-2078 · Source documented Interfaces & mixed-signal [## Garmo-USB3.2-PHY](https://garmolabs.com/ip/garmo-usb3-2-phy) USB router and PHY-control architecture with a release-specific compliance and analog boundary. Evaluation package IP-2094 · Source documented Compute & AI [## Garmo-VEC-DSP](https://garmolabs.com/ip/garmo-vec-dsp) AI/DSP Compute — 1024-bit deterministic vector DSP Evaluation package IP-2068 · Source documented ## Your next big idea. Let’s build it together. Start with a chip, a software release or a single IP block. [Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers)