--- title: Garmo-SRAM-Compiler | Garmo Labs url: https://garmolabs.com/ip/garmo-sram-compiler description: Memory IP — node-adaptable SRAM compiler architecture --- [Ip](https://garmolabs.com/marketplace) › IP-2091 Memory & storage # Garmo-SRAM-Compiler Memory IP — node-adaptable SRAM compiler architecture Evaluation package [Request evaluation](https://garmolabs.com/contact?products=ip-ip-2091) Gar Memory & storage THE TECHNICAL ROLE ## A clear integration boundary. Garmo-SRAM-Compiler integration role: Memory IP — node-adaptable SRAM compiler architecture. Documented composition: Bank/word/bit partition search driven by PPA and aspect-ratio constraints; Redundant row/column repair, MBIST/BISR and SECDED option; Retention, light/deep sleep, power gating and per-bank clock gating. 01 Bank/word/bit partition search driven by PPA and aspect-ratio constraints 02 Redundant row/column repair, MBIST/BISR and SECDED option 03 Retention, light/deep sleep, power gating and per-bank clock gating TECHNICAL OVERVIEW ## The details matter. [Download the product brief](https://garmolabs.com/static/briefs/ip-ip-2091.pdf) Canonical identity IP-2091 Responsibility Memory IP — node-adaptable SRAM compiler architecture Documented interface architecture compiler manifest + generated Verilog model/Liberty/LEF/GDS contract; runtime SRAM ports Documented building blocks Bank/word/bit partition search driven by PPA and aspect-ratio constraints; Redundant row/column repair, MBIST/BISR and SECDED option; Retention, light/deep sleep, power gating and per-bank clock gating Delivery boundary Evaluation / IP scope Evidence scope Evaluation package Architecture targets · not measurements 64 B to 16 MiB generated macros; 1RW/1R1W/2RW families; ECC/repair/retention options. ### Before integration. Garmo-SRAM-Compiler integration role: Memory IP — node-adaptable SRAM compiler architecture. Documented composition: Bank/word/bit partition search driven by PPA and aspect-ratio constraints; Redundant row/column repair, MBIST/BISR and SECDED option; Retention, light/deep sleep, power gating and per-bank clock gating. - Interface version and parameter set - Clock/reset domains and integration constraints - Companion memory, PHY and software requirements - Verification collateral and acceptance criteria The selected release must confirm: - Node/library binding - Clock/reset limits - Physical and protocol dependencies - Artifact hashes - Acceptance criteria Unpublished values are not inferred from family names or architecture targets. [Discuss the integration](https://garmolabs.com/contact?products=ip-ip-2091) Evaluation package ## Know the release. Know what it establishes. Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing. This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow. [Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/ip-ip-2091) ### Release-specific qualification No node-port, silicon-performance, standards certification or analog qualification is inherited from a related product. Canonical record: P1 / REPRESENTATIVE ARCHITECTURE RTL — concrete integration specification and synthesizable RTL shell/representative datapath only; all frequency, throughput, power, area, jitter and standards-superiority figures remain architecture targets until the required evidence hierarchy closes. A PATH THAT FITS THE PROJECT ## Build with Garmo-SRAM-Compiler. Technical scope, rights, support and release configuration are agreed before delivery. evaluation ### Evaluate an individual IP configuration Inspect the named release and establish technical fit. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2091&scope=evaluation) production ### Named-design production license Agree deployment or design rights, deliverables and support. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2091&scope=production) custom ### Node binding or derivative integration Define the customer-specific work and acceptance criteria. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2091&scope=custom) ## Keep exploring. Memory & storage [## KENBE 512-bit Compare / Filter Near-Memory](https://garmolabs.com/ip/kenbe-512-bit-compare-filter-near-memory) 512-bit bounded compare/filter engine. RTL + models IP-4009 · Source / reference evidence Memory & storage [## KENBE 512-bit XOR Reduction Near-Memory](https://garmolabs.com/ip/kenbe-512-bit-xor-reduction-near-memory) 512-bit XOR/reduction datapath for guarded near-memory work. RTL + models IP-4011 · Source / reference evidence Memory & storage [## KENBE Atomic Commit](https://garmolabs.com/ip/kenbe-atomic-commit) Controls bounded atomic transaction-group commit/abort. RTL + models IP-4031 · Source / reference evidence ## Your next big idea. Let’s build it together. Start with a chip, a software release or a single IP block. [Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers) CANONICAL EVIDENCE RECORD · IP-2091 ### Source documented A concrete source or implementation record exists; the selected evidence does not establish complete qualification. **Record integrity and qualification boundary**Retained exact-release source reference; no new table locator was inferred. Evidence ranking for evaluation prioritization; not a probability or certification. [How evidence priority is determined ](https://garmolabs.com/marketplace/evidence)