--- title: Garmo-RV32-EC | Garmo Labs url: https://garmolabs.com/ip/garmo-rv32-ec description: CPU — high-efficiency RISC-V MCU core --- [Ip](https://garmolabs.com/marketplace) › IP-2071 Compute & AI # Garmo-RV32-EC CPU — high-efficiency RISC-V MCU core Evaluation package [Request evaluation](https://garmolabs.com/contact?products=ip-ip-2071) Gar Compute & AI THE TECHNICAL ROLE ## A clear integration boundary. Garmo-RV32-EC integration role: CPU — high-efficiency RISC-V MCU core. Documented composition: 2-wide fetch/decode with decoupled branch unit and 16-entry return stack; Physical memory protection, machine/user modes, optional MMU-lite; 32/64 KiB I/D cache options or deterministic TCM. 01 2-wide fetch/decode with decoupled branch unit and 16-entry return stack 02 Physical memory protection, machine/user modes, optional MMU-lite 03 32/64 KiB I/D cache options or deterministic TCM TECHNICAL OVERVIEW ## The details matter. [Download the product brief](https://garmolabs.com/static/briefs/ip-ip-2071.pdf) Canonical identity IP-2071 Responsibility CPU — high-efficiency RISC-V MCU core Documented interface architecture Harvard I/D memory, AXI/AHB adapter, debug, CLINT/PLIC/AIA option, TCM Documented building blocks 2-wide fetch/decode with decoupled branch unit and 16-entry return stack; Physical memory protection, machine/user modes, optional MMU-lite; 32/64 KiB I/D cache options or deterministic TCM Delivery boundary Evaluation / IP scope Evidence scope Evaluation package Architecture targets · not measurements RV32IMAFDCB + optional 128-bit V; 2-wide in-order; >6 CoreMark/MHz target; <12-cycle interrupt entry. ### Before integration. Garmo-RV32-EC integration role: CPU — high-efficiency RISC-V MCU core. Documented composition: 2-wide fetch/decode with decoupled branch unit and 16-entry return stack; Physical memory protection, machine/user modes, optional MMU-lite; 32/64 KiB I/D cache options or deterministic TCM. - Interface version and parameter set - Clock/reset domains and integration constraints - Companion memory, PHY and software requirements - Verification collateral and acceptance criteria The selected release must confirm: - Node/library binding - Clock/reset limits - Physical and protocol dependencies - Artifact hashes - Acceptance criteria Unpublished values are not inferred from family names or architecture targets. [Discuss the integration](https://garmolabs.com/contact?products=ip-ip-2071) Evaluation package ## Know the release. Know what it establishes. Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing. This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow. [Explore the evidence center](https://garmolabs.com/evidence) [Qualification record](https://garmolabs.com/qualification/ip-ip-2071) ### Release-specific qualification No node-port, silicon-performance, standards certification or analog qualification is inherited from a related product. Canonical record: P0 / REPRESENTATIVE ARCHITECTURE RTL — concrete integration specification and synthesizable RTL shell/representative datapath only; all frequency, throughput, power, area, jitter and standards-superiority figures remain architecture targets until the required evidence hierarchy closes. A PATH THAT FITS THE PROJECT ## Build with Garmo-RV32-EC. Technical scope, rights, support and release configuration are agreed before delivery. evaluation ### Evaluate an individual IP configuration Inspect the named release and establish technical fit. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2071&scope=evaluation) production ### Named-design production license Agree deployment or design rights, deliverables and support. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2071&scope=production) custom ### Node binding or derivative integration Define the customer-specific work and acceptance criteria. [Discuss this scope](https://garmolabs.com/contact?products=ip-ip-2071&scope=custom) ## Keep exploring. Compute & AI [## NPJ SolveTile v1.0.0](https://garmolabs.com/ip/npj-solvetile-v1-0-0) Reusable solver/bitset/sparse tile binding lane ALU, popcount/zero-skip, descriptor FIFO and deterministic transport to a reference model and SV source. RTL + models IP-4276 · Source / reference evidence Compute & AI [## Garmo RISC-V Processor IP](https://garmolabs.com/ip/garmo-risc-v-processor-ip) CPU pipeline; cache/memory interfaces; MMU/TLB options; interrupt/debug; FPU/vector options; compiler/software support; verification/formal collateral; hardened physical views. Architecture IP IP-001 · Source documented Compute & AI [## Garmo-NPU-1024](https://garmolabs.com/ip/garmo-npu-1024) AI Compute — 1024 tensor-slice cloud/robotics NPU Evaluation package IP-2067 · Source documented ## Your next big idea. Let’s build it together. Start with a chip, a software release or a single IP block. [Talk to Garmo](https://garmolabs.com/contact) [Start exploring](https://garmolabs.com/developers) CANONICAL EVIDENCE RECORD · IP-2071 ### Source documented A concrete source or implementation record exists; the selected evidence does not establish complete qualification. **Record integrity and qualification boundary**Retained exact-release source reference; no new table locator was inferred. Evidence ranking for evaluation prioritization; not a probability or certification. [How evidence priority is determined ](https://garmolabs.com/marketplace/evidence)